1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a circuit and a method of driving sub-word lines of a semiconductor memory device.
2. Description of the Related Art
FIG. 1 is a circuit diagram illustrating a conventional sub-word line driving circuit of a semiconductor memory device, and is disclosed in a Korean Patent Laid-Open Publication No. 2004-54362.
Referring to FIG. 1, the sub-word line driving circuit drives a word line WL in response to control signals NWE, PXID, PXIDG and PXIB, and includes NMOS transistors MN1, MN2, MN3 and MN4. The main word line driving signal NWE is a signal driving a main word line that is included in the semiconductor memory device, and the sub-word line driving signal PXID is a signal driving a word line WL that is coupled to the main word line. The control signal PXIDG is a signal that is applied to a gate of the NMOS transistor MN3, and the control signal PXIB is an inverted signal of the sub-word line driving signal PXID. The control signal PXIB is applied to a gate of the NMOS transistor MN4, which has its drain coupled to the source of transistor MN2 and its source coupled to ground voltage supply VSS. The main word line driving signal NWE and the sub-word line driving signal PXID change from 0V to a boosted voltage VPP.
The sub-word line driving circuit operates as follows. When the main word line driving signal NWE is enabled, a boost node NB is charged to a voltage VPP-Vth. Then, when the sub-word line driving signal PXID is enabled, the boost node NB is charged to a voltage 2VPP-Vth by an overlap capacitance existing between a gate and a drain of the NMOS transistor MN2. Here, Vth denotes a threshold voltage of the NMOS transistor MN1. Therefore, the boosted voltage VPP is supplied to the word line WL through the NMOS transistor MN2. The NMOS transistor MN3 mainly serves to maintain the word line WL in logic “low” state when the main word line driving signal NWE is in logic “low” state and the sub-word line driving signal PXID is in logic “high” state.
FIG. 2 is a circuit diagram illustrating another conventional sub-word line driving circuit of a semiconductor memory device, and is disclosed in a Korean Patent Laid-Open Publication No. 2002-33883.
Referring to FIG. 2, an NMOS transistor MN3, the gate of which is connected to the drain of an NMOS transistor MN2, mainly serves to maintain a word line WL in logic “low” state when a main word line driving signal NWE is in logic “low” state and a sub-word line driving signal PXID is in logic “high” state.
When the main word line driving signal NWE is in logic “low” state and the sub-word line driving signal PXID is in logic “high” state, the voltage that should be applied to the gate of the NMOS transistor MN3 so as to turn on the NMOS transistor MN3 is lower than VPP. However, in the sub-word line driving circuit in FIG. 2, the sub-word line driving signal PXID, having a value of VPP, is applied to the gate of the NMOS transistor MN3.
FIG. 3 is a circuit diagram illustrating still another conventional sub-word line driving circuit of a semiconductor memory device, and is disclosed in a Korean Patent Laid-Open Publication No. 2002-33883. Referring to FIG. 3, VPP-Vth is applied to the gate of the NMOS transistor MN3 through an NMOS transistor MN5. In the sub-word line driving circuit having the structure in FIG. 3, the gate voltage that turns on the NMOS transistor MN3 so as to maintain a word line WL in logic “low” state is VPP-Vth when a main word line driving signal NWE is in logic “low” state and a sub-word line driving signal PXID is in logic “high” state. Accordingly, the sub-word line driving circuit shown in FIG. 3 consumes less VPP power than the circuit in FIG. 2.